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8-bit, 250 msps 3.3 v a/d converter AD9480 features dnl = 0.25 l s b inl = 0.5 lsb single 3.3 v su pply operation (3.0 to 3.6 v) power dissipati o n of 590 mw at 250 msps 1 v p-p an alog input range internal 1.0 v r e ference single-ended or differenti a l analog inputs lvds outputs ( a nsi 64 4 le vels ) power-down mode clock du ty cy cle stabilizer applic ati o ns digital oscillos c opes instrumentation and meas ure m ent communications: point-to-point radios pred istortion loops general description the AD9480 is a n 8-b i t, m o n o l i thic a n alog-t o-dig i tal con v er t e r o p t i mi ze d fo r hig h sp e e d an d l o w p o w e r co n s um p t ion. sma l l in size and e a sy t o us e , t h e p r o d uc t o p era t es a t a 25 0 ms ps co n v ersio n r a t e , wi t h exce l l en t l i n e a r i t y an d d y na mic p e r f or m a nc e ove r it s f u l l op e r a t i n g r a nge. t o minimize sys t em cos t an d p o w e r dis s i p a t ion, th e AD9480 in cl ude s a n in te r n a l r e fer e n c e and t r ack- an d - hold cir c ui t. t h e us er o n l y p r o v ides a 3.3 v p o wer s u p p l y a nd a dif f er en t i al en co de clo c k. n o ext e r n al r e fer e n c e o r dr i v er co m p on e n ts a r e r e q u i r e d f o r m a n y ap p l i c at i o n s . the dig i tal o u t p u t s a r e l v ds ( a ns i 644) com p a t ib le wi th a n opt i on of t w o s c o m p l e me n t or bi n a r y output f o r m a t . t h e output da ta b i ts a r e p r o v ide d in p a ral l e l fas h ion alo n g wi t h an l v ds o u t p u t c l o c k, w h ic h sim p lif i es da ta ca p t ur e . f a b r ica t ed on an ad van c e d b i cm os p r o c es s, th e AD9480 is a v a i la b l e i n a 44 -le a d s u r f ace- mo un t p a cka g e ( t qfp) s p e c i f i e d o v er t h e i n d u s t r i al t e m p era t ur e ra n g e ( ? 40 c t o +85 c). func tio n a l block di agram d7 ? d 0 (l vd s) (l vd s) vin+ vin? clk+ cl k ? vref sense dco+ dco- agnd drgnd drvdd avdd AD9480 lvdsbias pdwn s1 lvds clock mgmt t&h 8-bit adc pipeline core logic reference 16 8 04619-0-001 fi g u r e 1 . product highlights 1. sup e r i o r l i ne ar it y . a d n l o f 0.25 mak e s t h e ad9 480 s u i t a b le f o r in st r u m e n t a t ion an d m e asur e m e n t a p plic a t ion s . 2. p o w e r - do w n mo de. a p o w e r - do w n f u n c t i on ma y b e exer cis e d t o b r in g t o t a l co n s um p t io n do wn t o 15 mw . 3. l v ds o u t p u t s ( a ns i - 644). l v d s output s s i m p l i f y t i m i ng a n d i m prove noi s e pe rf o r m a n c e . rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed .
AD9480 rev. 0 | page 2 of 28 table of contents dc specifications ............................................................................. 3 digital specifications ........................................................................ 4 ac specifications .............................................................................. 5 switching specifications .................................................................. 6 timing diagram ........................................................................... 6 absolute maximum ratings ............................................................ 7 explanation of test levels ........................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 definitions ......................................................................................... 9 equivalent circuits ......................................................................... 11 application notes ........................................................................... 12 clocking the AD9480 ................................................................. 12 analog inputs .............................................................................. 12 volt age reference ....................................................................... 13 digital outputs ........................................................................... 14 output coding ............................................................................ 14 interleaving two AD9480s ........................................................ 14 data clock out ........................................................................... 14 typical performance characteristics ........................................... 15 AD9480 evaluation board ............................................................ 19 power connector ........................................................................ 19 analog inputs .............................................................................. 19 gain .............................................................................................. 19 optional operational amplifier ............................................... 19 clock ............................................................................................ 19 optional clock buffer ............................................................... 19 optional xtal ........................................................................... 19 volt age reference ....................................................................... 20 data outputs ............................................................................... 20 evaluation board bill of materials ............................................... 21 pcb schematics .............................................................................. 22 pcb layers ...................................................................................... 24 outline dimensions ....................................................................... 26 ordering guide .......................................................................... 27 revision history 7/04revision 0: initial version
AD9480 rev. 0 | page 3 of 28 dc specifications avdd = 3.3 v, drvdd = 3.3 v; t min = C40c, t max = +85c, a in = C1 dbfs, full scale = 1.0 v, internal reference, differential analog and clock inputs, unless otherwise noted. table 1. AD9480-250 parameter temp test level min typ max unit resolution 8 bits accuracy no missing codes full vi guaranteed offset error 25 c i ? 40 40 mv gain error 1 25 c i ? 6.0 6.0 % fs differential nonlinearity (dnl) AD9480bsuz-250 full vi ? 0.5 0.28 0.5 lsb AD9480asuz-250 full vi ? 0.85 0.35 0.85 lsb integral nonlinearity (inl) full vi ? 0.9 0.26 0.9 lsb temperature drift offset error full v 30 uv/ c gain error full v 0.03 %fs/ c reference full v .025 mv/ c reference internal reference voltage full vi 0.97 1.0 1.03 v output current 2 25 c iv 1.5 ma i vref input current 3 25 c i 100 ua i sense input current 2 25 c i 10 ua analog inputs (vin+, vin ? ) differential input voltage range (fs = 1) 4 full v 1 vpp common-mode voltage full vi 1.7 1.9 2.1 v input resistance 25 c i 8.6 10 10.7 k ? full vi 8.4 10 11.2 k ? input capacitance 25 c v 4 pf analog bandwidth, full power 25 c v 750 mhz power supply avdd full iv 3.0 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 v power dissipation 5 25 c v 590 mw power-down dissipation 25 c v 15 mw iavdd 5 full vi 145 156 ma idrvdd 5 full vi 34 38 ma power supply rejection ratio (psrr) 25 c v ? 4.2 mv/v 1 gain error and gain temperature coefficients are based on the adc only (with a fixed 1 v external reference and a 1 v p-p diff erential analog input). 2 internal reference mode; sense = agnd. 3 external reference mode; vref driven by external 1.0 v reference; sense = avdd. 4 in fs = 1 v, both analog inputs are 500 mv p-p and out of phase with each other. 5 power dissipation and current measured with ra ted encode and a dc analog input (outpu ts static). see figure 29 for active oper ation.
AD9480 rev. 0 | page 4 of 28 digital specifications avdd = 3.3 v, drvdd = 3.3 v; t min = C40c, t max = +85c, a in = C1 dbfs, full scale = 1.0 v, internal reference, differential analog and clock inputs, unless otherwise noted. table 2. AD9480-250 parameter temp test level min typ max unit clock inputs (clk+, clk ? ) differential input full iv 200 mvpp common-mode voltage 1 full vi 1.4 1.5 1.68 v input resistance full vi 4.2 5.5 6.0 k ? input capacitance 25 c v 4 pf logic inputs (pdwn, s1) logic 1 voltage full iv 2.0 v logic 0 voltage full iv 0.8 v logic 1 input current full vi 160 ua logic 0 input current full vi 10 ua input resistance 25 c v 30 k ? input capacitance 25 c v 4 pf digital outputs differential output voltage (v od ) 2 full vi 247 454 mv output offset voltage (v os ) full vi 1.125 1.375 v output coding full iv twos complement or binary 1 the common mode for clock inputs can be externally set, such that 0.9 v < clk < 2.6 v. 2 lvdsbias resistor = 3.74 k?.
AD9480 rev. 0 | page 5 of 28 ac specifications avdd = 3.3 v, drvdd = 3.3 v; t min = C40c, t max = +85c, a in = C1 dbfs, full scale = 1.0 v, internal reference, differential analog and clock inputs, unless otherwise noted. table 3. AD9480-250 parameter temp test level min typ max unit signal to noise ratio (snr) 25 c v 47 db 25 c i 45 47 db f in = 19.7 mhz f in = 70.1 mhz f in = 170 mhz 25 c i 45 46 db 25 c v 46.5 db 25 c i 44.8 46.5 db signal to noise and distortion (sinad) f in = 19.7 mhz f in = 70.1 mhz f in = 170 mhz 25 c i 44.8 46.5 db 25 c v 7.5 bits 25 c i 7.2 7.5 bits effective number of bits (enob) f in = 19.7 mhz f in = 70.1 mhz f in = 170 mhz 25 c i 7.2 7.5 bits 25 c v ? 65 dbc 25 c i ? 65 ? 60 dbc worst second or third harmonic distortion f in = 19.7 mhz f in = 70.1 mhz f in = 170 mhz 25 c i ? 65 ? 60 dbc 25 c v ? 70 dbc 25 c i ? 70 ? 63 dbc worst other f in = 19.7 mhz f in = 70.1 mhz f in = 170 mhz 25 c i ? 70 ? 63 dbc 25 c v ? 65 dbc 25 c i ? 65 ? 60 dbc spurious-free dynamic range (sfdr) 1 f in = 19.7 mhz f in = 70.1 mhz f in = 170 mhz 25 c i ? 65 ? 60 dbc two-tone intermodulation distortion (imd) f in1 = 69.3 mhz, f in 2 = 70.3 mhz 25 c v ? 68 dbc 1 nyquist bin energy ignored.
AD9480 rev. 0 | page 6 of 2 8 switching specifications a v d d = 3.3 v , d r vd d = 3.3 v ; dif f er en t i al en co de in p u t, un les s o t h e r w is e no t e d . table 4. a d 9 4 80-2 5 0 p a r a m e t e r t e m p t e s t leve l m i n t y p m a x u n i t f u l l v i 2 5 0 m s p s f u l l v i 2 0 m s p s f u l l i v 1 . 2 2 n s clock maximum conv ersion rate minimum conversion rate clock pulse wid t h high (t eh ) clock pulse wid t h low (t el ) f u l l i v 1 . 2 2 n s f u l l v i 1 . 9 n s f u l l v i 2 . 8 3 . 8 n s f u l l v 0 . 5 n s f u l l v 0 . 5 n s f u l l v i 1 . 9 2 . 7 3 . 7 n s f u l l i v 0 0 . 1 0 . 6 n s o u tput pa ram e ters val i d time (t v ) 1 propagation de l a y (t pd ) 1 rise time (t r ) 20% to 80% fall t ime ( t f ) 20% to 80% dco propagatio n delay (t cpd ) data-to-dco skew (t pd C t cpd ) pipeline latency 25 c v i 8 c y c l e s apertu r e aperture delay ( t a ) 25 c v 1 . 5 n s aperture uncertainty (j itter) 25 c v 0 . 2 5 p s r m s 1 val i d time is approximatel y equal to minimum t pd . c load equal s 5 pf maximum. timing diagram n? 1 n n+ 1 n+ 8 n+9 n +10 n+11 t eh t el 1/ f s t a n? 8 t pd 8 cycles t v n?7 n n+1 n+2 t cpd cl k+ cl k? da ta out dc o? dc o+ ai n 04619-0-002 f i g u re 2. ti ming d i ag r a m
AD9480 rev. 0 | page 7 of 2 8 absolute maximum ratings ther mal im p e da n c e ( ja ) = 46.4 c/w (4-la y er p c b) table 5. parameter min rating max rating electr ical avdd (with respect to agnd) ? 0.5 v 4.0 v drvdd (with respect to drgnd ) ? 0.5 v 4.0 v agnd (with respect to drgnd ) ? 0.5 v 0.5 v digital i/o (with respect to drgnd ) ? 0.5 v drvdd + 0.5 v analog inputs (with respect to agnd) ? 0.5 v avdd + 0.5 v environ m en tal operating temperature ? 40 c 8 5 c j u nction temperature 150 c case temperatu r e 150 c storage temperature 150 c explanation of test levels table 6. l e v e l d e s c r i p t i o n i 100% production tested. ii 100% production tested at 25 c and guaranteed by design and characterizati on at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical va lue only. vi 100% production tested at 25 c and guaranteed by design and characterizati on for industrial temperature range. s t r e s s es a b o v e t h os e lis t e d u n de r t h e a b s o l u t e m a xim u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD9480 rev. 0 | page 8 of 2 8 pin conf iguration and fu nction descriptions 1 2 3 4 5 6 7 8 9 10 11 12 clk ? avdd agnd d0_c (lsb) drgnd drvdd clk+ d0_t (lsb) d1_c d1_t d2_c 33 32 31 30 29 28 27 26 25 24 23 agnd avdd agnd drgnd s1 pdwn sense d7_t (msb) d7_c (msb) d6_t d6_c d 2_t 13 d 3_c 14 d 3_t 15 drgnd 16 dco? 17 dco+ 18 drv dd 19 d 4_c 20 d 4_t 21 d 5_c 22 d 5_t pin 1 nc = no connect 44 agnd 43 nc 42 lv ds bias 41 av dd 40 agnd 39 vin + 38 vin ? 37 agnd 36 av dd 35 agnd 34 vr ef AD9480 top view (not to scale) 04619-0-003 f i gure 3. pin config ur ation ta ble 7. pi n f u nct i on d e s c ri pt i o ns pin no. name description pin no. name description 1 clk+ input clockt r ue 23 d6 _c data output bit 6complement 2 clk ? input clockc o mplem e nt 24 d6 _t data output bit 6true 3 avdd 3.3 v analog supply 25 d7_c da ta output bit 7complement (msb ) 4 a g n d a n a l o g g r o u n d 2 6 d 7 _ t data output bit 7true ( m sb) 5 drvdd 3.3 v digital output supply 27 drgnd digital ground 6 d r g n d d i g i t a l g r o u n d 2 8 s 1 data format select and duty cycle stabili z er selection. see . 7 d0_c data ouput bit 0complement ( l s b ) 2 9 p d w n power-down se l e c t i o n 8 d0_t data output bit 0true (l s b ) 3 0 a g n d a n a l o g g r o u n d 9 d1_c data output bit 1compleme nt 31 avdd 3.3 v analog supply 10 d1_t data output bit 1true 32 agnd analog ground 11 d2_c data output bit 2complement 33 sens e reference mode selection. see table 9. 12 d2_t data output bit 2true 34 vref voltage reference input/ output 13 d3_c data output bit 3comple m e n t 3 5 a g n d analog g r o u n d 14 d3_t data output bit 3true 36 avdd 3.3 v analog supply 15 drgnd digital ground 37 agnd analog ground 16 dco ? data clock outputcomplement 38 vin ? analog inputcomplem e nt 17 dco+ data clock outputtrue 3 9 v i n + a n a l o g i n p u t t r u e 18 drvdd 3.3 v digital output supply 40 agnd analog ground 19 d4_c data output bit 4compleme nt 41 avdd 3.3 v analog supply 20 d4_t data output bit 4true 42 lvds bias lvds outpu t cu rrent adjust 21 d5_c data output bit 5compleme nt 43 avdd 3.3 v analog supply 22 d5_t data output bit 5true 44 agnd analog ground
AD9480 rev. 0 | page 9 of 2 8 definitions ana l og b a n d w i d t h the a n alog in pu t f r e q uen c y a t w h ich t h e s p e c t r al p o w e r o f t h e f u ndam e n t a l f r e q uen c y (as de t e r m in e d b y t h e fft a n a l y s is) is re d u c e d by 3 d b . ap e r t u r e d e l a y the dela y b e tw e e n t h e 50% p o i n t o f t h e r i sin g e d g e o f t h e en c o de co m m a nd and t h e i n st an t t h e a n a l o g in p u t is sa m p l e d . ap e r t u r e un c e r t a i n t y ( j i t t e r ) the s a m p le-t o-s a m p le va r i a t ion in a p er t u r e dela y . c l o c k pu ls e w i d t h/d u ty cy cl e pulse w i d t h h i g h i s th e m i ni m u m a m o u n t o f tim e tha t t h e c l ock p u ls e s h o u l d b e lef t in a l o g i c 1 s t a t e t o achi e v e ra t e d p e r f o r ma n c e; pu ls e wi d t h lo w is t h e mini m u m t i me clo c k p u ls e s h o u ld b e lef t in a lo w s t a t e . s e e timin g im p l ica t io n s o f c h a n g i n g t eh in t h e s e c t ion clo c kin g t h e AD9480. a t a g i v e n c l o c k r a t e , t h es e sp e c if i c a t i o n s def i n e an ac cep t a b le clo c k d u ty c y cle. cr o s s t alk c o u p lin g o n t o o n e c h a n n e l be in g dr i v en b y a l o w le v e l ( ? 40 dbfs) sig n al w h en t h e ad jacen t in ter f er in g cha n n e l is dr i v en b y a f u l l -s cale sig n al . d i f f erenti a l a n a l o g i n put re si st anc e , d i f f erenti a l a n a l o g i n put c a p a c i t a nc e, an d d i f f erenti a l a n a l o g input i m p e d a n c e the r e a l an d com p lex im p e dances m e asur e d a t e a ch a n a l o g in p u t p o r t . t h e r e sist a n c e is m e asur e d st a t i c a l ly a nd t h e ca p a c i t a n c e an d dif f er en t i al in pu t im p e dan c es ar e m e as ur e d wi t h a n e tw o r k a n a l y z er . d i f f erenti a l a n a l o g i n put v o lt a g e r a ng e the p e a k -t o - p e ak dif f er en t i al vol t a g e t h a t m u st b e a p plie d t o t h e con v er t e r t o g e n e r a t e a f u l l - s cale r e s p o n s e . p e ak dif f er en t i a l v o l t a g e is com p u t e d b y obs e r v i n g t h e v o l t a g e on a sin g le p i n a nd sub t r a c t i n g t h e vol t a g e f r o m t h e o t h e r p i n, w h ich is 180 o u t o f p h as e . p e ak t o p e a k dif f er en tial is com p u t ed b y r o ta t i n g th e in p u ts p h as e 180 an d t aking th e p e ak m e asur em en t a g ain. then t h e dif f er en ce is com p ut e d b e twe e n b o t h p e ak me a s u r e m e n t s . d i f f erenti a l n o n l i n e a r i ty t h e devia t i o n o f a n y cod e w i d t h f r o m a n id eal 1 l s b s t e p . eff e ct i v e n u m b e r o f b i ts the ef fe c t i v e n u m b er o f b i ts (e n o b) is calc u l a t e d f r o m t h e m e as ur ed s i n a d ba se d o n t h e eq ua ti o n (as s u m i n g full - s cal e in p u t) 6.02 db 76 . 1 ? = measured sinad enob f u ll - s c a le i n p u t p o w e r e x p r ess e d i n dbm. c o m p ute d u s in g t h e fol l o w in g e q u a t i on: ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 001 . 0 log 10 2 input fullscale fullscale z rms v power ga in er r o r g a i n e r r o r i s th e d i f f e r e n ce betw ee n t h e m e a s ur ed a n d id eal f u l l -s cale i n p u t v o l t a g e ra n g e o f t h e ad c. ha r m o n i c d i s t or t i on , s e c o n d the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e s e con d ha r m o n ic co m p on en t, rep o r t ed in db c. ha r m o n i c d i s t or t i on , t h i r d the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e th i r d h a rm o n i c co m p o n en t , r e p o r t ed i n d b c. in t e g r a l no n l i n e a r i t y the de v i a t ion of t h e t r a n sfer f u n c t i on f r o m a refer e n c e li n e m e as ur ed in f r ac tio n s o f 1 ls b usin g a bes t s t raig h t line det e r m i n e d b y a le as t s q ua r e c u r v e f i t. minim u m c o n v ersi on r a t e the e n co de ra te a t w h ich t h e snr o f t h e lo w e s t a n alog sig n al f r e q u e nc y d rop s by no more t h an 3 d b b e l o w t h e g u ar an te e d limi t. max i mu m c o n v er si on r a te the e n co d e ra te a t w h ich p a ramet r ic t e st in g is p e r f o r m e d . ou t p u t p r o p aga t io n d e la y the dela y b e tw e e n a dif f er en t i al cr os sin g o f clk+ an d c l k ? a n d t h e tim e w h en all o u t p u t da ta b i t s a r e w i t h i n v a lid logi c lev e ls. n o is e (f o r an y r a n g e w i thin t h e ad c) this val u e i n cl udes b o t h t h er mal a nd qua n t i za t i o n n o is e . ? ? ? ? ? ? ? ? ? ? = 10 10 001 . dbfs dbc dbm noise signal snr fs z v w h er e: z is t h e in pu t i m p e dance . fs is t h e f u l l s c a l e o f t h e de vi ce fo r t h e f r e q uen c y in q u es t i on. snr i s th e val u e f o r th e pa r t i c ula r i n p u t lev e l. sig n al is t h e sig n al le v e l w i t h i n t h e ad c r e p o r t e d i n db b e lo w full sc al e . po w e r s u p p l y r e j e c t i o n r a t i o the ra t i o o f a cha n g e i n i n p u t o f fs et v o l t a g e t o a cha n g e in po w e r s u p p l y v o l t a g e .
AD9480 rev. 0 | page 10 of 28 signal-to-noise and distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. it also may be reported in dbc (that is, degrades as signal level is lowered) or dbfs (that is, always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. it also may be reported in dbc (that is, degrades as signal level is lowered) or in dbfs (that is, always relates back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dbc. transient response time transient response time is defined as the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time out of range recovery time is the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
AD9480 rev. 0 | page 11 of 28 equivalent circuits vin+ 25k ? 16.7k ? 16.7k ? 150 ? 25k ? 1.2pf vin? 1.2pf avdd 04619-0-004 150 ? fi g u r e 4 . a n a l o g i n p u t s 04619-0-005 12k ? 150 ? 150 ? 12k ? 10k ? 10k ? c lk+ avdd clk ? fi g u r e 5 . c l o c k i n p u t s vdd 30k ? s 1 04619-0-006 fi g u r e 6 . s 1 i n p u t avdd 30k ? pdwn 04619-0-007 f i gure 7. p o w e r - d o wn input 1.2v 3.7k ? drvdd drvdd ilvds out lvdsbias k 04619-0-008 fi g u r e 8 . l v d s b i a s i n p u t 04619-0-009 v+ v+ dx+ drvdd dx? v? v? f i gure 9. l v ds d a t a , dc o o u tputs
AD9480 rev. 0 | page 12 of 28 appli c ation notes the AD9480 us es a 1.5 b i t p e r sta g e a r c h i t ec t u r e . the a n alog in p u ts dr i v e an in teg r a te d h i g h b a ndwi d t h t r ack-and- h o ld ci r c ui t th a t s a m p le s th e s i gn al p r i o r t o q u a n tiz a ti o n b y th e 8-b i t c ore. f o r e a s e of u s e, t h e p a r t i n clu d e s an o n - b o a rd re f e re nc e a nd i n p u t log i c t h a t acce p t s t t l, cmos, o r l v p e cl le ve ls. the dig i t a l o u t p u t log i c lev e ls a r e l v ds (ans i 644 c o m p a t i b le). clocking the AD9480 an y hig h s p e e d a/d con v er t e r i s ext r em e l y s e n s i t i v e t o t h e q u ali t y o f t h e s a m p lin g clo c k p r o v ide d b y t h e u s er . a t r ack-and- ho l d c i rc u i t i s e s s e n t i a l l y a m i x e r , and a n y noi s e, d i stor t i on , or t i min g ji t ter o n t h e clo c k is com b i n e d wi t h t h e desir e d sig n al a t t h e a/ d o u t p u t . c o n s idera b le c a r e has b e en t a k e n i n t h e desig n o f th e cl o c k in p u t o f t h e AD9480, a n d t h e us er is ad vis e d t o g i v e co mm ens u ra t e t h o u g h t t o t h e clo c k s o ur ce. the AD9480 has a n in t e r n al c l o c k d u ty c y c l e s t a b iliza t io n cir c ui t t h a t lo cks t o t h e r i sin g e d g e o f cl o c k a nd o p t i mi zes timin g in t e r n al l y f o r s a m p le ra tes betw een 100 ms ps an d 250 ms ps. this al lo ws f o r a wide ra n g e o f in p u t d u ty c y c l es a t t h e i n p u t w i t h ou t deg r adin g p e r f o r ma n c e . j i t t e r o n t h e r i sin g e d g e o f t h e in p u t is s t i l l o f p a ra m o u n t con c er n a nd is n o t r e d u ce d b y t h e i n t e r n al s t ab i l iza t io n cir c ui t. th e d u ty c y cle co n t r o l lo o p do es n o t f u n c tion f o r c l o c k ra t e s les s tha n 70 m h z n o mi n a ll y . th e loo p h a s a tim e co n s ta n t as soci a t ed wi th i t th a t n e e d s t o b e co nsider e d i n a p pli c a t ion s w h er e t h e clo c k ra te can c h a n g e dyna mical l y , r e q u ir in g a wai t tim e o f 5 s a f t e r a d y namic c l o c k f r eq u e n c y incr e a s e b e f o re val i d da ta is a v a i lab l e . the clo c k d u ty c y cle s t a b i l i z er ca n b e dis a b l e d a t p i n 28 (s1). the clo c k i n p u t s a r e in ter nal l y b i as e d t o 1.5 v ( n o m inal) an d s u p p o r t ei t h er dif f er en t i al o r sing le-e n d e d sig n a l s. f o r b e s t d y na mic p e r f o r ma nce, a d i f f er en t i a l sig n a l is r e co m m e n de d . a n m c 100l vel16 p e r f o r m s w e l l in the cir c ui t t o dr i v e the c l o c k in p u ts (ac co u p l i n g is o p t i o n al). i f t h e clo c k b u f f er is g r e a t e r t h a n 2 i n ch es f r o m t h e a d c, a s t anda r d l v p e cl t e r m ina t io n ma y b e r e q u ir e d in st e a d o f t h e sim p le p u l l -dow n t e r m in a t ion s h own in f i gur e 10. 04619-0-010 AD9480 clk+ 0.1 f 0.1 f 510k ? 510k ? pecl gate clk ? f i g u re 10. cl ock i ng t h e a d 9 4 80 analog inputs the a n alog in pu t t o t h e a d 948 0 is a dif f er en t i a l b u f f er . f o r b e s t d y na mic p e r f o r ma nce, im p e dan c es a t vi n+ and vin ? sh o u ld m a t c h . op ti m a l pe rf o r m a n c e i s o b ta in ed w h e n th e a n alog in p u ts a r e dr i v e n dif f er en t i al ly . s n r and s i n a d p e r f o r ma n c e ca n deg r ade if t h e analog in p u t is dr i v en wi t h a sin g le-e n d e d sig n a l . the a n a l og in p u ts s e lf- b i a s t o a p p r o x ima t e l y 1.9 v ; t h is co mm o n - m o d e v o l t a g e c a n b e ext e r n al ly o v e r dr i v en b y a p p r o x ima t e l y 300 mv if r e q u ir ed . a w i d e ba n d tra n s f o r m e r , s u c h a s th e m i n i ci r c ui t s ad t 1 - 1 w t , ca n p r o v i d e t h e dif f er en t i al a n al og in p u ts fo r a pplica t ion s t h a t r e q u ir e a sin g le - e n d e d -t o-dif f er en t i al con v ersio n . n o te t h a t t h e f i l t er a nd ce n t er -t a p ca p a c i to r on t h e s e conda r y side is o p t i o n a l a nd de p e n d e n t o n a p pli c a t io n re q u ir e m en ts. a n r c f i l t er a t t h e s e con d a r y side h e l p s r e d u ce an y wideb a nd n o i s e get t in g a l ias e d b y t h e a d c. 04619-0-011 AD9480 vin+ avdd (r, c optional) agnd 0.1 f 10pf 33 ? 49.9 ? 33 ? vin? f i g u re 11. d r iv ing t h e a d c w i t h an r f t r a n s f or me r f o r dc-co u p l ed a p p l ic a t ion s , th e ad8138 o r ad8351 ca n s e r v e as a con v e n ien t ad c dr i v er , dep e ndin g on r e q u ir e m e n ts. f i gur e 12 s h o w s a n exa m p l e wi t h the ad8138. the AD9480 pcb has an o p tio n al ad8351 on bo a r d , as sh o w n in f i gur e 41 a nd f i gur e 42. the ad8351 ty p i cal l y yie l ds bet t er p e r f o r ma n c e f o r f r eq uen c ies g r ea t e r tha n 30 mh z t o 40 mh z. 04619-0-012 AD9480 a d 81 38 vin+ avdd agnd 0.1 f 20pf 33 ? 33 ? vin? 49.9 ? 2k ? 1.3k ? 499 ? 499 ? 523 ? 499 ? f i g u re 12. d r iv ing t h e a d c w i t h t h e a d 81 3 8 table 8. s1 vol t age levels s1 voltage data format duty cycle sta b ilizer 0.9*avdd ? > a v dd offset binary disabl ed 2/3 avdd (0.1 *avdd) offset binary enabled 1/3 avdd (0.1 *avdd) twos complem e nt enabled agnd ? >(0.1*a v dd) t w os comp lem e nt disabl ed
AD9480 rev. 0 | page 13 of 28 the AD9480 can b e easil y co nf igur ed f o r dif f er en t f u l l -s cale ra n g es. s e e t h e v o l t a g e refer e nce s e c t ion fo r mo r e info r m a t io n. op ti m a l pe rf o r m a n c e i s a c h i ev ed w i t h a 1 v p-p a n alog i n p u t. 04619-0-013 sense = gnd vin+ 2.0v 500mv 2.0v vin? digitalout = all 1s digitalout = all 0s f i g u re 13. a n a l og i n put f u l l s c al e voltage r e ference a s t a b le an d acc u ra t e 1.0 v r e f e r e n c e is b u il t in to th e AD9480. u s ers c a n ch o o s e t h is in t e r n al r e fer e n c e o r p r o v ide a n ext e r n al re f e re nc e f o r g r e a te r a c c u r a c y a n d f l e x ibi l it y . f i g u re 1 5 show s t h e typ i cal r e feren c e va r i a t io n wi t h t e m p era t u r e . t a b l e 9 s u m m a riz e s th e a v a i la b l e r e f e r e n c e co n f i g ura t io n s . select logic adc core 0.5v 7k ? vref 0.1 f 10 f + sense vin+ vin ? 04619-0-014 7k ? f i gure 14. inte rn al r e fer e n c e equ i v a l e nt circuit fixed r e ference the i n t e r n al r e fer e n c e can b e c o nf igur e d fo r a dif f er en t i al s p an o f 1 v p-p (s ee f i gur e 17). i t is r e co mmen d e d to p l ace a 0.1uf c a pa ci t o r a s c l ose a s pos s i b l e t o th e vr e f p i n ; a 1 0 u f c a pa ci t o r i s also r e q u i r ed (see th e p c b la y o u t f o r g u i d a n ce ). i f th e i n t e rn al r e f e r e n c e o f th e AD9480 is us ed t o dr i v e m u l t i p le co n v er t e rs t o im p r o v e ga in ma t c hin g , t h e lo adin g o f t h e r e fer e n c e b y t h e o t h e r con v er t e rs m u s t b e co n s i d er e d . f i gur e 17 dep i c t s h o w t h e in t e r n a l r e fer e nce v o l t a g e is a f fe c t e d b y lo ading. temperature ( c) vr ef ( v ) 1.0085 1.0080 1.0075 1.0060 1.0055 1.0065 1.0070 1.0050 1.0045 1.0040 1.0035 ?40 ? 20 0 2 0 4 0 6 0 8 0 04619-0-049 f i gure 15. t y pic a l r e ferenc e v a r i ation with t e mper ature 04619-0-016 0.1 f 10 f vref sense f i gure 16. int e rn al f i x e d refer e n c e ( 1 v p -p) iref (ma) % change in v r e f v o ltage 0 ? 0.1 ? 0.2 ? 0.4 ? 0.3 ? 0.5 0 0.5 1.5 1.0 2.0 2.5 3.0 04619-0-017 f i g u re 17. inte rn al v r e f v s . l oad cur r ent ta ble 9. r e fere nce co nfi g ura t i o ns sense voltage resulting vref reference differentia l sp an avdd n/a (external reference input) extern al 1 x external refe rence voltage 0.5 v (self biased) 0.5 (1 + r1/r2) v prog rammable 1 vref (0. 75 v p-p to 1.5 v p-p) agnd to 0.2 v 1.0 v internal fixed 1 v p-p
AD9480 rev. 0 | page 14 of 28 external reference an ext e r n al r e f e r e n c e ca n be us ed f o r gr ea t e r accurac y a n d t e m p era t ur e s t ab ili t y w h en r e q u ir ed . th e ga in o f th e AD9480 ca n a l s o b e va r i e d usin g t h is conf igura t io n. a vol t a g e o u t p ut d a c can be us e d t o s et vref , p r o v idin g f o r a m e an s t o dig i tal l y ad j u s t t h e f u l l -s cale v o l t a g e . vref ca n be ext e r n al l y s et t o vo lt age s f rom . 7 5 v to 1 . 5 v ; opt i m u m p e r f or m a nc e i s t y pi c a l l y o b ta in ed a t vref = 1 v . (s ee th e t y p i cal p e rf o r m a n c e c h a r ac t e r i st ics s e c t io n.) 04619-0-018 may require rc filter avdd external reference or dac input vref sense f i g u re 18. e x ter n a l r e f e r e n c e programmabl e reference the p r og ra mma b le r e fer e n c e c a n b e us e d t o s e t a dif f er en t i al in p u t s p a n an y w her e between 0.75 v p-p an d 1.5 v p-p b y usin g a n ext e r n al r e sis t o r divider . th e s e n s e pin wi l l s e lf-b ias t o 0.5 v , a nd t h e r e s u l t ing vref is eq ual t o 0.5 (1 + r1/r2). i t is r e co mme n d e d to k e ep t h e su m o f r1+ r 2 10 k? to limit vref lo adin g ( f o r vref=1.5 v , s et r1 eq ual t o 7 k? a nd r2 eq ual t o 3.5 k?). 04619-0-019 0.1 f r1 r2 10 f vref sense f i g u re 19. p r og r a m m ab le r e f e rence digi tal ou tputs l v ds o u t p u t s ar e a v a i la b l e w h en a 3.7 k? rs et r e sis t o r is p l ace d a t pin 42 (l vds b i a s) t o g r o u n d . th e rs et r e sis t o r c u r r en t (~ 1.2 v/rs et) is ra t i o e d o n -chi p s e t t ing t h e o u t p ut c u r r en t a t each o u t p u t eq u a l t o a n o minal 3.5 ma wi t h an rs et o f 3.74 k?. v a r y in g t h e rs et c u r r en t als o lin e a r ly cha n g e s t h e l v d s output c u r r e n t , re su lt i n g i n a v a r i abl e output s w i n g f o r a f i xe d t e r m ina t ion r e sist an ce . a 100 ? dif f er en tial t e r m ina t ion r e sis t o r p l ace d a t t h e l v ds r e cei v er in p u ts res u l t s in a n o minal 350 mv s w in g a t t h e r e cei v er . l v ds m o de facil i ta t e s in t e r f acing wi t h l v ds r e ceiv ers in c u s t om a s i c s a nd fpg a s t h a t ha v e l v ds ca p a b i li ty fo r sup e r i or s w itch i n g p e r f or m a nc e i n noi s y e n v i ron me n t s . si ng l e p o in t-t o -p o i n t n et t o p o log i es a r e r e co mm ende d wi th a 100 ? t e r m ina t ion r e sis t o r as clos e t o t h e r e ce i v er as p o s s i b le . k e ep t h e t r ace len g t h 3 t o 4 in ch es maxi m u m and t h e di f f er en t i al o u t p ut tra c e le n g th s a s eq ual as pos s i b le . outpu t co ding table 10. code (vin+) ? (v in ? ) offset binary twos complement 255 > 0.512 v 1111 1111 0111 1111 255 0.512 v 1111 1111 0111 1111 254 0.508 v 1111 1110 0111 1110 ? ? ? ? ? ? ? ? 129 0.004 v 1000 0001 0000 0001 128 0.0 v 1000 0000 0000 0000 127 C0.004 v 0111 1111 1111 1111 ? ? ? ? ? ? ? ? 2 -0.504 v 0000 0010 1000 0010 1 C0.508 v 0000 0001 1000 0001 0 C0.512 v 0000 0000 1000 0000 0 < C0.512 v 0000 0000 1000 0000 interleaving two AD9480s in s t r u m e nt at i o n ap p l i c at i o n s m a y p r e f e r t o i n t e r l e a v e , o r p i n g -p o n g, tw o AD9480s t o ac hiev e twice t h e s a m p le ra te , o r 500 ms ps. i n t h es e a p p l ica t io n s , i t is im p o r t a n t to ma t c h t h e ga in and o f fs et o f t h e tw o ad c s . v a r y in g t h e r e fer e n c e v o l t a g e al lo ws t h e ga in o f t h e a d cs t o b e ad j u s t e d ; exter nal dc o f fs et c o m p e n s a t i on c a n b e u s e d to re d u c e of f s e t m i s m a t c h b e t w e e n tw o a d cs. th e s a m p ling phas e o f fs et b etwe e n t h e tw o a d cs is ext r em e l y i m p o r t a n t as we l l , a nd r e q u ir es v e r y lo w s k e w b e tw e e n clo c k s i g n als dr i v i n g t h e ad cs (< 2 p s clo c k sk e w fo r a 100 mh z a n alog in p u t f r eq uenc y). dat a cloc k ou t an l v ds da ta clo c k is a v ailab l e a t d c o+ an d d c o . th es e cl o c k s c a n f a c i l i t a t e l a tch i ng of f - ch ip , prov i d i n g a l o w ske w c l oc ki n g so l u ti o n . th e o n - c hi p d e la y o f th e d c o c l oc k s tra c k s wi t h t h e on chi p de l a y o f t h e da t a b i ts, (under simi la r lo ading) such t h a t t h e var i a t ion b e twe e n t p d and t c p d i s mini mi ze d . i t is r e co mme n d e d t o k e ep t h e t r ace len g t h s on t h e da t a an d d c o p i n s m a tch e d and to 3 to 4 i n ch es max i m u m. the o u t p u t and d c o o u t p uts sh o u ld b e desig n e d fo r a dif f er en t i al cha r ac ter is t i c im p e dan c e o f 1 00 ?, a n d t e r m i n a t e d dif f er en t i al ly a t t h e r e cei v er wi th 10 0 ?.
AD9480 rev. 0 | page 15 of 28 typical perf orm ance cha r acte ristics a v d d , d r vdd=3.3v , t = 25c, a in dif f er en t i al dr i v e , fs = 1, unles s o t h e r w is e n o t e d. mhz db 0 ?20 ?10 ?50 ?40 ?30 ?70 ?60 ?90 ?80 06 0 40 20 80 100 120 04619-0-020 snr = 46.2db h2 = 72.8dbc h3 = 73.2dbc sfdr = 69.8dbc f i g u re 20. fft : f s = 25 0 m s ps, a in = 10. 3 m h z @ ?1 dbfs mhz db 0 ?20 ?10 ?50 ?40 ?30 ?70 ?60 ?90 ?80 06 0 40 20 80 100 120 04619-0-021 snr = 46.1db h2 = 71.4dbc h3 = 74.3dbc sfdr = 68.7dbc f i g u re 21. fft : f s = 25 0 m s ps, a in = 70 mh z @ C 1 dbfs mhz db 0 ?20 ?10 ?50 ?40 ?30 ?70 ?60 ?90 ?80 06 0 40 20 80 100 120 04619-0-022 snr = 45.9db h2 = 67dbc h3 = 73.3dbc sfdr = 67dbc f i g u re 22. fft : f s = 25 0 m s ps, a in = 70, mh z @ C 1 dbfs , single -ended i n put mhz db 0 ?20 ?10 ?50 ?40 ?30 ?70 ?60 ?90 ?80 06 0 40 20 80 100 120 04619-0-023 snr = 45.9db h2 = 71.9dbc h3 = 67dbc sfdr = 67dbc f i g u re 23. fft : f s = 25 0 m s ps, a in = 170 mhz @ ?1 dbfs a in (mhz) db 90 85 80 75 70 65 60 55 50 45 40 0 5 0 200 250 100 150 300 350 400 04619-0-024 h3 h2 sfdr snr sinad f i gure 24. a n a l og i n put f r equenc y s w eep , a in = ? 1dbfs , fs=1v , f s = 25 0 m s ps h3 h2 sfdr sinad a in (mhz) db 80 75 70 65 60 55 50 45 40 0 5 0 200 250 100 150 300 350 400 04619-0-025 snr f i gure 25. a n a l og i n put f r equenc y s w eep , a in = ? 1 dbfs , fs =. 75 v , f s = 25 0 m s ps
AD9480 rev. 0 | page 16 of 28 sfdr snr sinad sample clock (mhz) db 75 70 65 60 55 50 45 40 0 5 0 150 200 100 250 300 04619-0-026 f i gure 26. snr, si n a d , sfdr vs. s a mple clock f r eq uenc y , a in = 7 0 m h z ? 1 db fs analog input drive level (dbfs) db 80 60 70 40 50 20 30 0 10 ?70 ? 60 ?40 ?50 ? 30 ? 2 0 ? 10 0 04619-0-027 sfdrdbfs sfdrdbc 65db ref line f i g u re 27. sfdr v s . a in input l e ve l; a in = 70 m h z a t 250 m s p s mhz db 0 ?20 ?10 ?50 ?40 ?30 ?70 ?60 ?90 ?80 06 0 40 20 80 100 120 04619-0-028 f1, f2 = ? 7dbfs 2f2-f1 = ? 71.1dbc 2f1-f2 = ? 68dbc f i g u re 28. t w o - t o n e int e r m odu l at io n d i s t o r t i on (69. 3 m h z and 70 .3 m h z; f s = 25 0 m s p s ) encode (msps) curre nt in ma 180 160 100 120 140 60 40 20 80 0 0 5 0 100 200 250 150 300 04619-0-029 i avdd i drvdd f i g u re 29. i av d d and i dr vdd vs. clock rate , c lo a d = 5 pf a in = 7 0 m h z @ C 1 dbfs dcs off dcs on clock positive duty cycle (%) db 50 49 48 47 46 45 43 42 41 44 40 20 30 40 50 60 70 80 046190-0-030 f i gure 30. snr, si n a d vs. clock p u lse w i dth high, a in = 70 m h z @ C1 dbfs, 25 0 msps, dcs on/ o ff external vref voltage (v) s nr, s i nad db 50.0 47.5 45.0 42.5 40.0 0.5 1.1 0.9 0.7 1.5 1.3 1.7 1.9 04619-0-031 snr sfdr 50 65 70 75 80 s f dr db sinad f i gure 31. snr, si n a d , and sfdr vs. v r ef in ex ter n al ref e r e nc e m o d e , a in = 70 m h z @ C1 dbfs, 25 0 msps
AD9480 rev. 0 | page 17 of 28 temperature ( c) gain error ( % ) 3 2 0 1 ?1 ?2 ?3 ?4 0 0 ?20 2 0 4 0 6 0 8 0 04619-0-032 fs = 1v ext ref fs = 1v int ref f i g u re 32. f u ll- s c al e g a in e r r o r v s . t e mpe r at u r e , a in = 70. 3 mh z @ C0.5 dbfs, 250 ms ps , fs= 1 temperature (c) db 75 65 70 60 45 50 55 40 ?40 ? 20 20 04 0 6 0 04619-0-033 8 0 sfdr 1v int ref sinad 1v int ref f i gure 33. sinad , s f dr vs. t e mper ature , a in = 70 m h z @ C1 dbfs, 25 0 msps avdd (v) change in vre f (%) 0.10 0 0.05 ?0.15 ?0.10 ?0.05 2.7 2.8 2.9 3.1 3.5 3.4 3.3 3.2 3.0 3.6 04619-0-034 f i g u re 34. v r e f s e ns it iv it y t o a v dd sinad avdd (v) db 70 65 60 55 50 45 3.0 3.1 3.2 3.3 3.4 3.5 3.6 04619-0-035 sfdr snr f i gure 35. snr, si n a d , and sfdr vs. s u p p ly v o ltag e , a in = 70. 3 m h z @ C 1 dbfs, 2 5 0 m s ps , code lsb 0.5 0.3 0.4 0 0.1 0.2 ?0.2 ?0.1 ?0.5 ?0.3 ?0.4 0 100 50 150 200 250 04619-0-036 f i g u re 36. t y pic a l d n l pl ot , a in = 1 0 . 3 m h z @ C 0 .5 dbfs, 25 0 m s ps code lsb 0.50 0.25 0 ? 0.50 ? 0.25 0 100 50 150 200 250 04619-0-037 f i g u re 37. t y pic a l i n l pl ot , a in = 1 0 . 3 mh z @ C 0 .5 dbfs, 25 0 ms ps
AD9480 rev. 0 | page 18 of 28 8 0 temperature (c) d e la y sen sitivity ( n s) 0.30 0.20 0.25 0.15 ?0.05 0 0.05 0.10 ?0.10 ?40 ? 20 20 04 0 6 0 04619-0-038 f i g u re 38. p r opag a t ion d e l a y adder v s . t e mpe r at u r e 0 100 200 300 400 500 600 700 800 900 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 vd if ( m v) v os (v ) 04619-0-039 02 4 6 8 1 0 1 2 1 4 rset (k ?) v os v od f i gure 39. l v ds o u tput s w ing , com m o n-mod e v o ltag e v s . rse t , pla c ed at l v dsb i a s
AD9480 rev. 0 | page 19 of 28 AD9480 evaluation board the AD9480 e v al ua t i o n bo a r d o f f e rs a n easy wa y t o t e s t t h e d e v i c e . i t r e q u i r e s a c l o c k s o u r c e , a n a n a l o g i n p u t s i g n a l , a n d a 3.3 v p o w e r s u pply . th e clo c k s o ur ce is b u f f er e d o n t h e b o a r d to p r o v ide t h e clo c ks fo r t h e ad c a nd a da t a -r e a dy sig n al. th e dig i t a l o u tp u t s and o u tp u t clo c k s a r e a v a i la b l e a t a 40-p i n co nne c t o r , p10. the b o a r d has s e ver a l dif f er en t m o de s o f o p era t ion an d is shi p p e d in t h e fol l o w in g co nf ig ura t io n: ? of fs et b i na r y ? i n te r n a l vo lt age re f e re nc e power connector p o w e r i s s u p p li e d t o th e boa r d vi a 2 de ta c h a b le 4- p i n po w e r st r i p s . table 11. pow e r connector t e r m i n a l c o m m e n t s avdd 1 3.3 v analog supply for adc ~ 150 ma drvdd 1 3.3 v output supply f o r adc ~ 40 ma vctrl 1 3.3 v supply for supp ort clock cir c uitry ~ 50 ma op amp, e x t. ref optional supply fo r op amp and adr510 reference 1 a v dd , dr vdd , and vc trl are the mi nimum required po w e r c o nnec t ion s . 2 l v el16 c l ock buff er can be po w e r e d fr om a v dd or vc trl l v el16 buff er j u m p er . analog inputs the e v al u a tion bo a r d accep t s a 700 mv p-p a n alog in p u t sig n a l cen t er e d a t g r o u nd a t s m b c o nn e c t o r j3. this sig n al is te r m i n ate d to g rou nd t h rou g h 5 0 ? b y r22. th e i n p u t can b e a l te r n a t iv ely te r m i n a t e d a t t h e t1 t r ans f or me r s e c o nd ar y b y r21 a nd r28. t 1 is a wi deb a nd rf t r a n sfo r m e r p r o v idin g t h e sin g le-e n d e d - t o-dif f er en t i al con v ersio n , al lo wing t h e ad c t o b e dr i v en dif f er en t i al ly , mini mi zing e v e n -o r d er har m o n ics. a n opt i on a l t r ans f or me r , t 4 , c a n b e pl a c e d i f d e s i re d ( r e m ove t 1 , a s s h ow n i n fi g u re 4 1 an d f i g u re 4 2 ) . the a n alog sig n al ca n be lo w-p a s s f i l t er e d b y r31, c8, a n d r29, c9 a t t h e a d c in p u t. gain f u l l s c ale is s et b y t h e s e ns e j u m p er . this j u m p er a p plies a b i as t o t h e s e n s e pin t o va r y t h e f u l l - s cale ra n g e; t h e defa u l t p o si t i o n i s se n s e = gr o u n d , se t t i n g t h e ful l sc al e t o 1 v p - p . optional operational amplifier the pcb has b e en desig n e d t o acco mm o d a t e an o p t i o n al ad8351 o p a m p whic h can s e r v e as a con v enien t s o l u tion f o r dc-co u p l ed a p p l ica t ion s . t o us e th e ad8351 o p a m p , r e m o v e r29, r31, a nd c3. p o p u la te r40, r43, a nd r47 wi th 25 ? r e sis t o r s, a n d p o p u la te c24, c2 8, c29, c30, c31, a n d c32 wi t h 0.1 uf ca p a ci t o rs. p o p u la te r38, r39, a nd r51 wi th a 10 ? r e sis t o r , a n d r4 4 a nd r45 wi t h a 1 k? r e sis t o r . p o p u la t e r41 wi t h a 1.2 k? r e sis t o r a nd r42 wi t h a 100 ? r e sis t o r . p o p u la te r52 wi th a 10 k? r e sis t o r . clock the clo c k i n p u t is t e rmin a t e d t o gr o u n d thr o ugh 50 ? at s m a c o nn e c t o r j1. th e in p u t is ac-co u ple d t o a high s p ee d dif f er en t i al r e ceiv e r (l v el16) t h a t p r o v id es th e r e q u ir e d lo w ji t t e r , f a s t ed g e r a t e s n eed ed f o r be s t p e rf o r m a n c e . j 1 in p u t s h o u ld b e > 0.5 v p-p . p o w e r t o t h e l v el16 i s s e t to v c trl (defa u l t ) o r a v d d b y j u m p er placem en t a t th e de vice . opt i o n al c l ock buffe r the pcb has b e en desig n e d t o acco mm o d a t e t h e s n l v ds1 lin e dr i v er . the s n l v ds1 is us e d as a hig h s p e e d l v ds -le v e l o p ti o n al en code c l oc k . t o use thi s c l oc k , p l ea se r e m o v e c 2 , c 5 , a nd c6. p l ace a 0.1 uf ca p a ci t o r o n c34, c35, and c26. p l ac e a 10 ? r e sis t o r o n r48 a nd p l ace a 100 ? r e sis t o r o n r6. p l ac e r49 a nd r53 wi th a 0 ? r e sis t o r . f o r bes t r e s u l t s usin g th e l v ds lin e dr i v er , j1 in p u t sh o u ld b e > 2 .5 v p-p . optional xtal the pcb has b e en desig n e d t o acco mm o d a t e an o p t i o n al cr ys tal os cil l a t or whic h ca n s e r v e as a con v enien t c l o c k s o ur c e . the fo o t p r i n t c a n acce p t b o t h t h r o u g h - h ole and s u r f ace- m o u n t de vices, in c l udin g v e c t r o n x o -400 a nd v e c t r o n v c c6 fa mil y oscilla t o r s. 04619-0-040 vcc vcc out ? out+ gnd fi g u r e 4 0 . x t a l fo o t p r i n t t o us e ei t h er cr ys tal , p o p u la t e c26 a nd c27 wi th 0.1 uf ca p a c i - t o rs. p o p u la te r49 a nd r53 wi t h 0 ? r e sis t o r s. p l ace r54, r55, r56, a nd r57 wi th 1 k? r e sis t o r s. re m o v e c6 and c5. i f t h e v e c t r o n v c c6 f a mi ly cr ys t a l is b e i n g us e d , p o pu la te r48 wi t h a 10 ? r e sis t o r . i f usin g th e x o -4 00 cr ys tal , p l ace j u m p er e21 o r e22 t o e23.
AD9480 rev. 0 | page 20 of 28 voltage reference the AD9480 has an internal 1 v reference mode. the adc uses the internal 1 v reference as the default when sense is set to ground. an optional on-board external 1.0 v reference (adr510) can be used by setting the sense jumper to avdd, by placing a jumper on e20 to e3, and by placing a 0 ? resistor on r36. when using an external programmable reference, (r20, r30) remove the sense jumper. data outputs the off-chip drivers provide lvds compatible output levels with an lvds rset resistor of 3.74 k?. the adc digital outputs can be terminated on the board by 100 ? resistors at the connector if receiving logic does not have the required termination resistance. (the on-chip lvds output drivers require a far-end 100 ? differential termination.)
AD9480 rev. 0 | page 21 of 28 evaluation board bill of materials table 12. no. quantity reference designator device package value 1 23 c1, c2, c3, c4, c5, c6, c10, c11, c12, c17, c18, c19, c20, c21, c22, c23, c26, c27, c28, c31, c32, c33, c35 capacitor 0402 0.1 uf 2 1 c13 capacitor tant (3528) 10 uf 3 4 c7, c14, c15, c16 capacitor tant (6032) 10 uf 4 2 j1, j3 sma 5 2 p12, p13 4-pin power co nnector post z5.531.3425.0 wieland 6 2 p12, p13 4-pin power detachable connector 25.602.5453.0 wieland 7 2 r22, r27 resistor 0603 50 ? 8 8 r2, r3, r4, r5, r7, r8, r9, r10, and r15 (not placed) r42 resistor 0603 100 ? 9 6 r1, r44, r45, r50, r58, r59 resistor 0603 1000 ? 10 1 r41 resistor 0603 1200 ? 11 3 r40, r43, r47 resistor 0603 25 ? 12 2 r38, r39, r51 resistor 0603 10 ? 13 2 r25, r26 resistor 0603 130 ? 14 1 r23, r24 resistor 0603 510 ? 15 1 r32, r34 resistor 0603 82 ? 16 2 r29, r31 resistor 0603 zero ? 17 2 r33, r52 resistor 0603 10 k? 18 1 r63 resistor 0603 3.74 k? 19 1 t1 transformer cd542 minicircuits t1-1wt 20 1 u13 ad8351 msop-10 21 1 u2 sn65lvds1 sn65lvds1 dbv not placed 22 1 u14 adr510 sot-23 not placed 23 1 u15 vcc6pecl6 vcc6-qab-250m000 not placed 24 1 u1 xo-400 dip4(14) not placed 25 1 u12 AD9480 tqfp-44 26 1 u11 mc100lvel16d s08nb 27 1 t2 etc1-1-13 1-1 tx not placed 28 11 c8, c9, c24, c25, c29, c30, and c34 (all not placed) capacitor 0402 not placed 29 20 r6, r20, r21, r28, r30, r36, r46, r48, r49, r51, r55, r56, and r57 (all not placed) resistor 0603 user-determined 30 16 e73, e74, e75, e76, e77, e78, e79, e80, e81, e82, e83, e84, e17, e5, e6, e7, e8, e35 jumper
AD9480 rev. 0 | page 22 of 28 pcb sche matics agnd avdd cl k+ cl k? clk+ clk ? clk clkinput d3 t d4 c d3 c d4 t d2 t d5 c d2 c d5 t d1 t d6 c d1 c d6 t d0 t d7 c d0 c d7 t dco+ dco ? drgnd drvdd agnd nc pw dn s1 lvdsbias sense vin+ vin ? vref drvdd drgnd avdd agnd avdd agnd drgnd avdd agnd agnd agnd gnd 1 234 5 6 789 1 0 1 1 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 6 5 4 1 2 3 12 13 14 16 17 18 19 20 21 22 15 u1 2 AD9480 d5 c d5 t d6 c d6 t d7 c d4 t dr+ d4 c dr? d3 t d3 c d2 t d2 c d1 t d0 t gnd drvdd gnd s1 pw dn avdd gnd gnd drvdd gnd avdd d0 c d1 c d7 t gnd avdd gnd gnd gnd avdd gnd r2 100 ? r3 100 ? r4 100 ? r5 100 ? r1 5 100 ? r7 100 ? r9 100 ? r1 0 100 ? r8 100 ? r6 x p1 p1 0 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p1 8 p1 9 p2 p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p2 8 p2 9 p3 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 p3 8 p3 9 p4 p4 0 p5 p6 p7 p8 p9 c 40ms gnd g nd 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 5 6 7 8 9 p1 0 d1 t d2 t d3 t d4 t d5 t d6 t d7 t gnd dr ? gnd dr+ gnd d7 c d6 c d5 c d4 c d3 c d2 c d1 c d0 c gnd d0 t output data conn. p1 p2 p3 p4 p1 p2 p3 p4 avdd vctrl 1 2 3 4 p1 2 ptmicro4 1 2 3 4 p1 3 ptmicro4 gnd gnd drvdd gnd vamp gnd pow e r conn. pads for shorting el1 6 , for op amp configuration remove resistors r2 9 , r3 1 , and c3 probe points c3 3 0. 1 f p1 5 p1 4 p6 p7 p1 7 p1 6 clkn clk d? d+ e8 3 e8 4 e7 9 e8 2 e8 0 e8 1 e7 8 e7 7 gnd gnd gnd gnd gnd gnd gnd gnd gnd e3 5 e1 2 e3 2 e7 0 e4 avdd avdd gnd vctrl for on board ext. ref j u mper e1 3 to 1 4 and e2 0 to e3 place r3 6 0 ? and r3 3 1 0 k ? trim/nc v? v+ adr510 3 2 1 u1 4 + c1 3 10 f gnd vctrl gnd gnd gnd gnd cm cm c1 2 0. 1 f c1 0. 1 f r2 0 xx r3 0 xx r3 6 x gnd r2 5 130 ? r2 7 50 ? r2 4 510 ? r2 3 510 ? r3 4 82 ? vctrl gnd gnd r2 8 x r2 1 x e1 5 e1 6 vctrl ampout ampin ampout vam p e2 0 e 3 e1 7 e1 7 e1 7 e7 e9 e1 1 e1 0 e8 e1 3 e1 4 e2 e1 r3 6 1k ? optional r6 3 3. 7k ? r3 3 10k ? extvref r3 1 00 r2 9 00 gnd gnd avdd vctrl c8 x c1 0 0. 1 f c4 0. 1 f c1 0 0. 1 f gnd gnd c9 x gnd c1 1 0. 1 f tin1 cm gnd t1 + t1 + cm t1 ? t1 ? optional transformer 6 5 4 1 2 3 j3 j1 r2 2 50 gnd gnd analog input gnd clk clkn q r vbb vcc vee q 100lvel16 2 3 7 1 4 8 5 6 u1 1 c1 1 0. 1 f c6 0. 1 f c5 0. 1 f r3 2 82 ? vctrl gnd r2 6 130 ? 04619-0-041 f i g u re 41. pcb s c h e m a t i c (1 of 2)
AD9480 rev. 0 | page 23 of 28 gnd vcc z d y sn65lvds1 optional + inhi inlo pwup rgp1 rpg2 comm ophi oplo vocm vpos optional xtals optional x= not normally populated xx = user selected, is not normally populated c35 0.1 f c23 0.1 f c7 10 f out? out+ p4 p3 vam p x r38 r48 x x c34 u1 xo-400 vcc 6 pecl6 out vcc vee ?out 8 14 7 1 e36 r59 1k ? r58 1k ? r50 1k ? e34 6 3 4 8 7 1 2 5 10 9 u13 ad8351 2 5 1 3 4 u2 avdd gnd c20 0.1 f c19 0.1 f c18 0.1 f c17 0.1 f + c16 10 f vivis v ampf gnd c32 0.1 f + c14 10 f drvdd gnd c22 0.1 f c21 0.1 f c27 x ampout ampout gnd c25 x + c15 10 f vctrl gnd e24 e25 e27 e29 s1 e26 vctrl gnd e28 e30 e31 gnd gnd vampf pwdn vctrl avdd gnd out+ ampin clkinput vctrl gnd gnd clk? clk+ gnd gnd gnd out+ 5 6 4 2 1 3 r41 x r42 x r40 x r46 x r45 x r44 x r51 x c31 x c30 x r39 x r49 x r53 x r57 x r56x c23 x e22 e21 avdd e23 vctrl vctrl gnd vctrl r54 x r55 x c29 x c24 x c28 0.1 f gnd vampf vampf r52 x 04619- 0- 042 f i g u re 42. pcb s c h e m a t i c (2 of 2)
AD9480 rev. 0 | page 24 of 28 pcb layers 04619-0-043 f i g u re 43. pcb t o p - side s ilk s c r e en 04619-0-044 f i gure 4 4 . p c b t o p - si de co p p er r o uti n g 04619-0-045 f i gure 45. pcb gro u nd laye r 04619-0-046 f i g u re 46. pcb spl i t p o wer plan e
AD9480 rev. 0 | page 25 of 28 04619-0-047 f i gure 4 7 . p c b bo tto m - s i de c o p p er routi n g 04619-0-048 f i g u re 48. pcb bot t o m-s i de si lk s c reen
AD9480 rev. 0 | page 26 of 28 outline dimensions 1 33 34 44 11 12 23 22 0. 45 0. 37 0. 30 0. 8 0 bs c 10. 0 0 sq 12.00 sq 1. 20 ma x 0.75 0.60 0.45 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3. 5 0 0.15 0.05 view a rotated 90 ccw view a pin 1 compliant to jedec standards ms-026acb top v ie w (pins down) f i g u re 49. 4 4 -l ead thin plas t i c q u ad flat p a ck ag e [ t qfp ] (su - 44) di me nsio ns sho w n i n mi ll im e t e r s
AD9480 rev. 0 | page 27 of 28 ordering guide model temperature range description package option AD9480bsuz-250 1 , 2 ? 40 c to +85 c tqfp su-44 AD9480asuz-250 1 ? 40 c to +85 c tqfp su-44 AD9480-lvds/pcb 3 evaluation board 1 z = pb-free part. 2 optimized differential nonlinearity. 3 evaluation board shipped with AD9480bsuz-250 installed.
AD9480 rev. 0 | page 28 of 28 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04619C0C 7/04(0)

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